1. Field of the Invention
The present invention relates generally to a data holding circuit using, e.g. a latch circuit, and more particularly to a data holding circuit in which the probability of malfunction due to a soft error is reduced.
2. Description of the Related Art
With development in fine patterning of an LSI device, a charge representing 1 bit decreases. This leads to the increase in the possibility of occurrence of soft errors or soft error rate. Beyond 65 nm technology node, it is important to improve soft error tolerance.
In general, LSI circuits are classified into two groups: memory circuits and logic circuits. In the case of the memory circuit, soft errors can be suppressed effectively by adding a redundant bit to the data stored in the circuit. However, an effective countermeasure to soft errors, which is applicable to the logic circuit, has not yet been established.
The logic circuits can be classified into combinational logic circuits and data holding circuits. In the case of the combinational logic circuit, even if data temporarily upsets, it restores to the initial state unless data in the preceding stage upsets. Thus, soft errors in the combinational logic circuits have the small effect on the circuit operation. On the other hand, in the case of the data holding circuit, if data once upsets, it never restores until the right data is rewritten. Thus, soft errors in the data holding circuits are the serious in the operation.
As a general countermeasure to soft errors in the data holding circuit, a majority voting circuit has been proposed (see, e.g. Mark P. Baze, Steven P. Buchner, and Dale McMorrow, “A digital CMOS Design Technique for SEU Hardening”, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, p. 2603, December 2000). The majority voting circuit, however, requires an odd number (at least three) of identical circuits. In addition, a circuit determining which output is right is also required. These lead to the significant increase in the chip area. Under the circumstances, there has been a demand for a data holding circuit that has a high tolerance to soft errors, while suppressing an increase in chip area.